The technical field relates to timing analysis systems, and, in particular, to static timing analysis of a digital circuit.
A wide variety of design verification tools are required to produce a working integrated circuit from a functional specification. These tools analyze different parameters of a circuit design to insure that the circuit will function properly after the circuit is fabricated. One important set of verification tools includes timing analysis tools, which are widely used to predict the performance of very large scale integrated (VLSI) designs. Often, timing analysis determines the best path for a designer to pursue or helps to optimize the overall circuit design. In digital circuits, timing considerations can be critical to proper performance. Timing analysis tools may be either static or dynamic.
Dynamic timing analysis (DTA) tools provide the most detailed and accurate information obtainable concerning the performance of a circuit. With DTA, a design engineer must provide sets of waveforms to simulate the conditions under which a circuit will operate. This type of timing analysis is often generated through simulation of a circuit by simulation programs that operate at the transistor level. Examples of such circuit simulation programs are SPICE by University of California at Berkeley and ASTAP by IBM Corporation. For more information on SPICE, refer to xe2x80x9cSPICE2: A Computer Program to Simulate Semiconductor Circuits,xe2x80x9d by L. W. Nagel, Technical Report ERL-M520, UC-Berkeley, May 1975. These DTA programs typically operate by solving matrix equations relating to the circuit parameters, such as voltages, currents, resistances and capacitances. Additionally, such circuit simulation approaches to performance analysis are pattern-dependent, or stated another way, the possible paths and the delays associated with the paths depend upon a state of a controlling mechanism or machine of the circuit being simulated. Thus, the result of a DTA depends on the particular test pattern, or vector, applied to the circuit.
While such circuit simulation programs and DTA tools provide high accuracy, long simulation times are required because a large number of patterns must be simulated since the best and worst case patterns are not known before the simulation occurs. The number of simulations which must be performed is proportional to 2n, where xe2x80x9cnxe2x80x9d is a number of inputs to the circuit being simulated. Thus, for circuits having a large number of inputs, DTA is not always practical.
Static timing analysis (STA) tools are also widely used to predict the performance of VLSI designs. In STA, a design engineer applies signal arrival and departure times only at each block input, not at base waveform. Additionally, each signal is assumed to switch independently in each machine cycle, i.e., static timing analyzer is waveform independent and simulates the most critical arrival time at each node in the circuit.
In STA, since only the best and worst possible rising and falling times are computed for each signal in the circuit, such times are typically determined in a single pass through a topologically-sorted circuit. When referring to a topologically-sorted circuit, a signal time associated with each subcircuit of the circuit being tested is determined in a sequential nature. Therefore, the signal time associated with a first subcircuit whose output will be propagated to a second subcircuit must be determined before the signal time associated with the second subcircuit is calculated. Typical static analysis methods are described in xe2x80x9cTiming Analysis of Computer Hardware,xe2x80x9d by Robert B. Hitchcock, Sr., et al., IBM J. Res. Develop., Vol. 26, No. 1, pp. 100-105 (1982).
Timing models used in timing analysis are blocks of computer data that can be used to recreate the timing behavior of an electronic circuit. The size of timing models should be as small as possible for a given complexity of circuit, while maintaining the accuracy of the timing model. In general, a smaller timing model will not only require less space in a computer memory, but also will be faster for a computer to evaluate. Often, timing model accuracy is sacrificed to shrink the timing model and speed its evaluation. This is especially important for large timing models that represent an entire subcircuit of an electronic system.
A popular technique for shrinking a timing model involves creating port-based timing models as opposed to path-based timing models. Port-based timing models analyze an electronic circuit to isolate and maintain only the timing behavior that can be observed at the circuit""s connections, often referred to as ports, to surrounding circuits. Any timing behavior of a circuit that is internal to the circuit is discarded, leaving only the information that is essential to verifying the timing behavior of the circuit in the context of surrounding circuits. The port-based timing models have been used in both timing simulation and STA. The timing models are accurate, and generally provide good compression of timing model size.
In port-based timing modeling, the electronic circuit is analyzed to determine the longest time for an electronic signal to pass from each input port to each output port. Often the shortest time is determined as well. An edge triggered latch in the circuit, controlled by a clock signal, acts much like an internal port and is also considered a start point and an end point for electronic signals. At the instant the value of its clock signal changes, the edge triggered latch passes the value of its data signal to its output signal. At other times, the edge triggered latch holds the value of its output signal constant. Analysis is also done to determine the longest time for an electronic signal to pass from each input port to the input signals of each edge triggered latch and from the output signal of each edge triggered latch to each output port.
In true port-based timing models, the internal latch nodes are abstracted away and only the longest time for an electronic signal to arrive at each given output port is calculated. Often the shortest time is calculated as well. The latest (and often also the earliest) allowed time for signal to arrive at each given input port is also calculated. For circuits with edge triggered latches, these calculations are rather simple. The longest time for a signal to arrive at the output port is the time when the clock signal changes on the edge triggered latch that is connected to the output port by a combinational circuitry, plus the time the signal passes from the latch to the output port. If more edge triggered latches are connected to the output port by a combinational circuitry, the latest signal arrival from all the latches is considered. The latest allowed time for the signal to arrive at the input port is the time when the clock signal changes on the edge triggered latch that is connected to the input port by a combinational circuitry, minus the time the signal passes from the input port to the latch, minus the setup time for the latch (due to the physical characteristics of the latch electronic circuitry, the signal value at the latch input must be stable before the clock signal changes). If more latches are connected to the input port by a combinational circuitry, the latest time for the signal to arrive at the input port is the minimum from the latest times determined for the individual latches as described above. The latch that determines the minimum time is referred to as the most critical latch. PathMill""s Black box timing model supports these calculations. However, the calculations become more complicated for circuits that use level triggered latches, and PathMill""s Black box cannot accurately model such circuits.
Many digital circuits use level triggered latches, i.e., transparent latches, in place of edge triggered latches. Like an edge triggered latch, a level triggered latch is controlled by a clock signal. The edge triggered latches are active only at the instant the clock signal changes, while the level triggered latches can be active at any time that the clock signal remains at a specified voltage (high or low voltage).
The level triggered latches in a circuit can time borrow amongst themselves. Time borrowing is possible when the combinational logic between two latches requires more time than the clock phase to compute a stable value. However, if the logic following the second latch requires less than an entire clock phase to compute a stable value, then the value propagated by the first latch need not become stable until some time after the second latch becomes active. The second set of logic will still have enough time to propagate a stable value, even though the calculations did not begin until some time after the latches become active. Time borrowing is an essential technique for latch-based design. High performance or custom designed circuits, such as modern CPUs, rely on level triggered latches to take advantage of the time borrowing that helps reach high clock frequencies. Timing models that do not support time borrowing are inadequate for such designs.
When the clock signal transitions to inactivate the latch, the level triggered latch latches the input data and holds that value on the output port until the clock transitions again. The input data is fed to the level triggered latch via the latch""s data pin. The output of the latch is available on the latch""s output pin. The clock signal is connected to the latch using the latch""s clock pin.
Due to the physical characteristics of the electronic circuitry from which physical latches are implemented, the transition between when the latch is transparent and when the latch holds its value is not instantaneous. Therefore, the value on the data pin must be available a certain amount of time before the clock signal transitions to a low voltage. This time is called the setup time. Routines that verify that the data is available early enough to meet the setup time are called setup checks and violations are called setup violations. In addition to the setup time, the data value must remain constant for a certain amount of time after the clock transitions to low. This time is called the hold time. Routines that verify that the data is available long enough to meet the hold time are called hold checks and violations are called hold violations. If a setup or a hold violation occurs, the latch might not contain a valid value. Thus, it is important that timing models accurately represent setup and hold times.
In a timing model block for a circuit, a signal arriving at the output ports depends on the signal arrival time at the input ports, referred to as stimulus. In a stimulus dependent timing model, the parameters of the timing model are limited to certain intervals of the arrival times. If the stimulus is outside of the interval, the timing model does not properly represent the circuit and the model needs to be rebuilt each time when the stimulus change. In a stimulus independent timing model, the timing model works irrespective of when the signal arrives at the input ports, i.e., always generating correct arrival at the output port.
Currently available timing models that can be input into general STA tools fall into three categories. PathMill""s conventional Black box timing models are port-based and stimulus independent. However, the conventional Black box timing models do not support transparency. PathMill""s new transparent Black box timing models are port-based with limited support of transparency. However, the new Transparent Black box timing models are stimulus dependent. PathMill""s Gray box timing models support transparency and are stimulus independent. However, the Gray box timing models are not port-based.
For circuits with level triggered latches, the Transparent Black box timing models are significant improvement over the conventional Black box timing models. The latest allowed time for the signal to arrive at a given input port, i.e., the time before setup violation occurs, is calculated, considering not only the first latch connected to the given input port by a combinational circuitry. The second latch or other sequential element that is connected to the first latch by a combinational circuitry is also considered, as well as the third and any successive latch that may be on a transparent path from the given input port. Considering all latches is important because, in circuits with transparent latches, the second, third, or other latch on the transparent path from an input port may be more critical than the first latch, i.e., the second, third, or other latch determines the latest time on the input port before the setup violation occurs, employing similar calculation procedure as described earlier for the first latch in the conventional Black box timing model. Similarly, the longest time for an electronic signal to arrive at the output port is calculated, considering not only the last latch connected to the output port by a combinational circuitry, but also the previous latch that is connected to the last latch by a combinational circuitry, as well as any earlier latch that may be on a transparent path to the output port.
However, in the Transparent Black box timing model, the signal arrival at the output port on a transparent path is correct only for the input port stimulus that was used to build the model. When the input stimulus changes, the model needs to be rebuilt or the signal arrivals at output ports on transparent paths may be wrong, since the Black box timing model cannot represent the unique clock-controlled connectivity between the input and the output ports on a transparent path. Instead, the output signal arrival time on the most critical transparent path is hard-coded in the model, which makes the model valid only for a particular input stimulus.
PathMill""s Gray box timing models support transparency and are stimulus independent. However, Gray box timing models abstract only combinational circuit elements and retain all sequential elements that are represented by internal clock-controlled nodes connected by time-arcs, i.e., not port-based. For blocks with a large number of latches, Gray box timing models have a large number of internal nodes and time-arcs, resulting in a large number of timing checks to be performed and a large number of paths to be traced in a STA run. All timing checks carried out on a lower level of hierarchy need to be repeated again on higher hierarchy levels, because no sequential nodes are abstracted away when moving from one level of hierarchy to the next level. As a result, the large number of timing checks leads to long STA runtimes and large memory requirements, especially on higher hierarchy levels and full chip levels, which, in turn, results in slow roll-up/roll-down times and a need to manually simplify the timing model so that the STA on larger blocks does not run out of memory.
A method for modeling a circuit block with a minimal level sensitive timing abstraction model includes extracting a plurality of parameters from a circuit that includes sequential elements, such as latches or domino logic, controlled by clock elements and creating an echo-circuit that represents the plurality of parameters. The echo-circuit is lightweight and can be input into any static timing analysis (STA) tools.
The extracted parameters are modeled by circuit elements in the echo-circuit as follows. A required time parameter, which represents the latest/earliest time a signal can arrive at a given input port before a setup/hold violation occurs on a circuit element in the modeled circuit, is modeled in the echo-circuit by a setup/hold check node attached to a corresponding input port. A valid time parameter, which represents the latest time a signal from any clock element in the modeled circuit arrives at the output port, is modeled in the echo-circuit by a derived clock node that controls a dummy latch node attached to a corresponding output port. An input-to-output delay parameter, which represents a time delay a signal passes from the input port to the output port on a path through transparent latches in the modeled circuit, is modeled in the echo-circuit by a time-arc (or by a net with delay) that connects the setup/hold check node attached to the input port and the dummy latch node attached to the output port. An input-to-output delay parameter, that represents a time delay a signal passes from the input port to the output port on a combinational path in the modeled circuit, is modeled in the echo-circuit by a time-arc (or by a net with delay) that connects the input port and the output port.
The dummy latch node enables the signal in the timing abstraction model to propagate from the input port to the output port only if the signal arrives at the output port later than a clock signal from the most critical clock element associated with that output port, i.e., the clock element from which signal in the modeled circuit arrives at the output port at the latest time.
In an embodiment, the setup/hold check node may be replaced by a latch node, denoted as setup/hold check latch, to assure proper cycle count advancement on a transparent path going from a given input port to a given output port. In another embodiment, more than one setup/hold check (or latch) node may need to be attached to each input port and more than one dummy latch node may need to be attached to each output port in circuits where the clock signals are derived from multiple reference clocks or from different phases of the same reference clock.
The timing abstraction model supports multiple levels of hierarchy and limits timing analysis to the most critical paths, i.e., a path from the input port to the setup/hold check node, a path from the input port to the dummy latch node, a transparent path between the input port and the output port, and a path between the most critical clock element and the output port, leading to significant reduction of the number of internal clock-controlled nodes, which in turn results in significant speed-up of STA runs on large circuits and reduced memory and storage space requirements. The number of internal nodes in the timing abstraction model scales with number of ports rather than with number of paths. For most circuits, the number of timing checks to be performed is limited to one check per each input port plus one check per each input port-output port pair that is connected by a transparent path for at least one input stimulus. Further speed-up of STA runs is achieved by tracing only the most relevant transparent paths to a given output port, i.e., only those paths on which signal arrives at the output port later than the latest clock signal, which reduces the number of paths fed to the adjacent blocks. The timing abstraction model also simplifies the output from the timing analysis and may shorten designer""s time to analyze STA results.